To safeguard circuits in an integrated circuit chip from electrostatic discharge, a device is included in the integrated circuit chip for protection during an electrostatic discharge event. Such protection can prevent damage from high voltage or current transients. Metal oxide semiconductors field effect transistors (MOSFETs) are particularly vulnerable to electrostatic discharge because an electrostatic discharge event can damage the gates of the MOSFETs, especially those with thin gate oxides.
The trend in semiconductor manufacture continues to be the reduction of the size of the overall I/O area on an integrated circuit and to enable a larger number of I/O pins on an integrated circuit chip. Unfortunately, the largest percent of the I/O area is used by the electrostatic protection devices. Accordingly, to increase the number of I/Os on the overall integrated circuit, the size of the ESD protection devices and, hence, the I/O area of the ESD devices must be reduced without affecting the protection of the non-ESD devices.
ESD NMOSFETs are commonly used as ESD protection devices. The required characteristics of the NMOSFET based protection devices are: low trigger voltage (Vt1), high failure current (It2) and low on-resistance (Ron). In order to reduce the size of the ESD protection device and still meet the ESD protection requirements, the failure current of the ESD NMOSFET needs to be increased and the on-resistance needs to be decreased compared with prior art devices. This, in turn, would enable a reduction in the device width and, therefore, a reduction in the area of the ESD device. Substrate triggering techniques are commonly used to reduce the trigger voltage, increase the failure current and lower the on-resistance.
A basic prior art device for electrostatic discharge (ESD) protection is shown in FIG. 1 and is a n-channel MOSFET between the input pad and the substrate and closely coupled to ground. To enhance the protection capability of this prior art device, a further prior art technique employs a lateral NPN transistor integral within a n-channel MOSFET. This ESD device is used to shunt to ground a large transient by turning on the lateral NPN when the event occurs. Another prior art technique also uses a lateral NPN transistor but it is coupled to the input element and operates to activate when the input element voltage exceeds threshold, the threshold being greater than or equal to the ordinary operating voltage of the circuitry coupled to the input element. However, none of these prior art structures will provide sufficient ESD protection when the area of the protection device is reduced in size, such as by as much as about 20 percent.